The new IDM (Integrated Device Manufacturer) 2.0 strategy was announced by Intel CEO Pat Gelsinger last year when he returned. Intel wants to manufacture chips for companies all over the world rather than just its own. It has recently made significant investments in the RISC-V ecosystem and has pledged to provide customers with x86 designs for licensing.
Customers will be able to get both hard and soft versions of various CPU cores from Intel in the future. A “soft” core is a programmable logic (FPGA)-based CPU core that is often implemented in an FPGA. A CPU core that is implemented in physical silicon is known as a “hard” core. Hard cores are the most common type of chips sold by AMD and Intel.
As a “chiplet chassis,” Intel envisions a chiplet design with x86, ARM, and RISC-V all co-existing on the same physical silicon as the chiplet design we mentioned last week. Intel believes there will be a long-term market for these types of products, according to Bob Brennan, VP of customer solutions engineering at Intel Foundry Services (IFS), with each IP dedicated to a specific type of best-fit workload.
In the chiplet chassis, we expect there will be demand for Arm and RISC-V, depending on which customer it is, and will support both. We have not fully developed our strategy, but the concept is similar in that we want to enable the ecosystem of IP around our products.— Bob Brennan, VP of customer solutions engineering, Intel Foundry Services (IFS)
The future of Intel’s Hybrid
Despite the fact that Intel has produced a number of non-x86 CPUs over the years, the terms “intel” and “x86” have become almost synonymous. The company’s statements of support for RISC-V and ARM emphasize that it is redefining itself.
Intel envisions a world where different microarchitectures are used for different tasks by chip designers. A vendor could use multiple RISC-V cores as dedicated I/O accelerators in this scenario, but with an x86 server CPU core and an ARM security processor in the background.
A low-power x86 CPU with an even lower-power RISC-V AI accelerator could be developed by another company.
Last year at Hot Chips, Esperanto, one of Intel’s recently announced RISC-V partners, discussed such an accelerator.
Intel has released a number of hybrid x86 CPUs with low- and high-power cores on the same silicon in the last year. A more advanced version of the same concept is to combine x86, ARM, and RISC-V silicon in a single package and connect the cores via chiplets.
The vision of Intel is a radical departure from the status quo. SoCs that mixed and matched microarchitectures have never been done before in this way by companies.
By mixing and matching CPU ISAs and connecting hardware via chiplets, the argument is made that GPU computing is conceptually similar to how CPU computing has augmented and expanded workloads that were previously only available to CPUs.
This type of consolidation may be encouraged by long-term trends in the semiconductor industry. As the number of chips in a chip increases, it becomes less expensive to pack more advanced functions into the same space.
An array of constantly active generalist cores draws less power than a slew of specialized accelerators that only light up occasionally.
Making assumptions work
Customers have use cases where multiple ISAs make sense, according to Intel’s argument. This is an unproven theory. Customers who want to build a chip that supports x86, ARM, and/or RISC-V in the same package have yet to be announced by Intel.
Intel’s aggressive foundry expansion and plans to support multi-ISA manufacturing are linked. Intel believes that controlling the manufacturing of CPUs is critical to its long-term success and profitability.
Intel has the best chance of winning business from the widest range of customers by supporting multiple ISAs.
With packaging, lithography, and integration options that aren’t available anywhere else, IFS wants to be the foundry of choice for cutting-edge customers. Intel must create a chiplet ecosystem that supports ISA integration in order to sell it as a distinct feature.
On two nodes, Intel intends to introduce multi-ISA technology. Intel 16 is the first (formerly known as Intel 22FFL). During Intel’s first foundry push, it was a more relaxed 14nm node that was originally intended for Intel customers.
When Intel launches what it now calls Intel 3, it will also bring this capability to the market. Intel 3 is roughly where we’d expect a hypothetical Intel 7nm+ to be in terms of Intel’s old nomenclature. IFS can market its services to a wider clientele with a wider range of use cases and products by using a mix of mature and cutting-edge nodes.
It’s possible that Intel’s long-term success will be determined by how well its customers accept the idea of multi-ISA devices. Although it’s not the most common practice, the concept could be in line with long-term semiconductor integration trends.